The invention is directed to integrated circuits, and more specifically to improved output driver circuits in integrated circuits manufactured using CMOS technology.
Integrated circuits which operate as logic circuits, including such LSI and VLSI circuits as microprocessors, microcomputers, and memories, present digital logic signals at their output. The desired output waveform of the transition of such digital logic signals going from a "0" logic state to a "1" logic state, or vice versa, is a step function, i.e., a square transition occurring in zero time. A rapid transition providing sufficient sink or source current is desired, of course, since the faster that an output circuit can provide a transition, the faster the receiving circuit can respond to the transition. However, the realization of such a logic transition in actual circuits provides a waveform having a non-zero rise or fall time, and having varying degrees of overshoot and undershoot, such overshoot and undershoot appearing not only at the output terminal, but also as noise on the power supply nodes and buses. Generally, as the desired speed of operation of circuits performing digital logic functions increases, the amplitude of such overshoot and undershoot increases, causing the circuit designer to make a tradeoff between the switching speed (and drive capability) of an output buffer circuit versus the amplitude of the noise generated by the output buffer circuit.
It is further useful, especially in VLS1 logic circuits, to provide digital output in a parallel manner, i.e., a plurality of digital output signals occurring at approximately the same time. In such a parallel arrangement, it is convenient to share power supply buses among the individual output buffers in order to conserve chip area. However, the sharing of power supply buses among output buffer circuits allaows the overshoot and undershoot at the power supply node of a switching output buffer to couple to the power supply node of a neighboring output buffer which is not switching. If the amplitude of the switching noise is sufficient, disruption of the output of the non-switching buffer may occur. In addition, circuits other than output buffers may also be sharing the power supply buses, and therefore may be disrupted by the switching noise of an output buffer. As a result, the trend of incorporating more and more logic functions into single integrated circuits, said functions necessarily being closer together, increases the sensitivity of integrated circuits to switching noise.
In addition, many such circuits are preferably constructed using CMOS (complementary metal-oxide-semiconductor) technology, because of the reduced power consumption and increased switching speed of digital logic circuits using CMOS technology. The use of CMOS in the construction of logic circuits further provides the ability to incorporate more logic functions into a semiconductor device of a given size, further increasing the amplitude of, and sensitivity to, such outpuyt overshoot and undershoot.
Prior techniques for dealing with this problem have included the use of separate ground nodes in an n-channel push-pull MOS output buffer, one of said ground nodes for sinking current during the initial transition from a high output state to a low output state, and the other for sinking DC current during the steady state condition of a low output state. Such an output buffer is shown and described in "A LAN System Interface Chip with Selectable Bus Protocols", by Donald Walters, Jr. et al., 1985 Digest of Technical Papers, 1985 IEEE International Solid-State Circuits Conference (IEEE, 1985), pp. 190-191. The separate ground nodes allow the DC ground node to sink output current without having the undershoot associated with the original transition coupled to it. However, the use of n-channel technology inherently precludes the circuit described in this paper from driving a "1" logic state to the full level of the biasing power supply, since the n-channel pull-up transistor will turn off as the output terminal of the circuit reaches a voltage greater than the blasing power supply voltage less a transistor threshold voltage. While further prior techniques have provided the use of a transistor in series between the output terminal and the drain of the pull-down transistor to damp the undershoot generated by a high-to-low transition, such a technique is ineffective for low-to-high transitions; if used in the pull-up side of an NMOS output buffer, the n-channel pull-up transistor would switch off a even a lower voltage, further reducing the drive level and increasing the switching time.
It is therefore an object of this invention to provide an output buffer circuit, useful in integrated circuits performing digital logic functions, which provides a fast logic transition in both directions, with overshoot and undershoot greatly reduced over prior output buffer circuits.
It is a further object of this invention to provide an output buffer which is capable of driving the output terminal fully to the voltage of the biasing power supply, but with reduced overshoot.
It is a further object of this invention to provide an output buffer which, when used in a parallel arrangement with other such output buffers, will isolate the power supply nodes of those output buffers which remain in a given output state from the noise created by neighboring output buffers which are making a logic transition.
It is a further object of this invention to provide an output buffer circuit manufacturable using CMOS technology.
It is a further object of this invention to provide an output buffer circuit which allows for the output waveform to be shaped in such a manner as to reduce the radio frequency interference (RFI) emanating from an integrated circuit using said output buffer.
Other objects and benefits of this invention will be apparent to those skilled in the art, based upon the description to follow herein.